In recent years, semiconductor memories using resistive elements as memory elements, such as magnetoresistive random access memory (MRAM), phase-change random access memory (PCRAM), and resistive random access memory (ReRAM), have attracted much attention and have been extensively developed. An ReRAM is a semiconductor memory which stores data by using change in resistance of a resistive memory element caused by applying a pulse voltage to the resistive memory element. At present, however, the ReRAM is still at a stage in which many models and materials are proposed for the storage mechanism thereof, and has been researched and developed by numerous manufacturers. A PCRAM is a semiconductor memory which stores data by using change in resistance of a resistive memory element caused by phase change of the crystalline structure of the resistive memory element as a result of passing a write current through the resistive memory element.
An MRAM is a semiconductor memory which stores data by using the magnetoresistive effect, in which resistance changes in accordance with the relative magnetization direction between a recording layer and a fixed layer, by using, as a memory element, a magnetoresistive element having a magnetic tunnel junction (MTJ) structure in which an insulating film is held between two ferromagnetic layers, the magnetization direction of one ferromagnetic layer (fixed layer) is fixed, and the magnetization direction of the other ferromagnetic layer (recording layer) is made reversible. In particular, the MRAM has the merit of nonvolatility, fast operability, high integration, and high reliability, and thus is expected as a memory device which can replace the SRAM, pseudo-SRAM (PSRAM), and DRAM.
In the prior art, a write method using a current induction magnetic field is commonly adopted as the write method of an MRAM. This is a write method in which the magnetization direction of the recording layer is reversed by a magnetic field induced by a current flowing through a write line. An MRAM adopting the current induction magnetic field method has problems such as a large write current due to being an indirect write method, and an increase in write current due to the increase in reversal magnetic field necessary for magnetization reversal of the recording layer caused by scaling down of the magnetoresistive element. As means for solving the problems, a spin-transfer MRAM using magnetization reversal by a polarization spin current has attracted attention and has been developed. In a spin-transfer MRAM, a current (reversal threshold current) necessary for spin-transfer magnetization reversal is determined by a current density flowing through the magnetoresistive element, and thus the reversal threshold current reduces as the area of the magnetoresistive element is reduced. Specifically, since the reversal threshold value is subjected to scaling, the spin-transfer MRAM is expected as technique which can realize a semiconductor memory of large capacity.
In a spin-transfer MRAM, a write is performed by causing a write current exceeding the reversal threshold value to flow through the magnetoresistive element, and data polarity thereof is determined by the direction of the write current flowing through the magnetoresistive element. For example, in common memory cells of 1Tr+1MTJ (1T1R) type, one end of an MTJ element is connected to a bit line, the other end of the MTJ element is connected to one source/drain electrode of a transistor (Tr), and the other source/drain electrode of the transistor is connected to a bit line different from the bit line to which the MTJ element is connected, and a gate electrode of the transistor is connected to a word line. In such a cell structure, the transistor is required to have a current driving capacity exceeding the reversal threshold current of the MTJ element. However, it is technically difficult to reduce the reversal threshold current of the MTJ element, and there are cases where the current driving capacity of the transistor is not sufficient for a write to the MTJ element.
In addition, it is desirable that a gate width (W) of a transistor forming a memory cell is formed with a minimum feature size (F) from the viewpoint of reducing the chip size. However, since the current driving capacity of a transistor depends on the gate width, and there are cases where it is inevitable to increase the gate width of the transistor. In such cases, there is the problem that the layout area of a memory cell increases, and the chip size increases, too. In addition, although it is desirable that the resistance of the MTJ element is small in view of reading and writing, the resistance of the whole memory cell, that is, the rate of the channel resistance of the transistor occupying the sum of the channel resistance of the transistor and the resistance of the MTJ element increases when the resistance of the MTJ element is reduced. This causes the problems that the influence of fluctuations in the channel resistance of the transistor during a read is increased, and that a read signal magnitude from the memory cell is reduced.
As means for solving the problems, a 2T1R cell structure obtained by adding a transistor to the conventional 1T1R structure has been proposed (for example, Japanese Patent No. 4157571). A 2T1R cell has a structure in which the transistor of a conventional 1T1R cell is replaced by two transistors connected in parallel. Adopting this structure doubles the current driving capacity, and reduces the channel resistance by half. However, since one transistor is added to the conventional structure, it has the problem that the layout area of a memory cell is increased.
In addition, as means for reducing the layout area of a memory cell, a method of sharing a bit line between adjacent columns, that is, a bit line pair, has been proposed (for example, Jpn. Pat. Appln. KOKAI Pub. No. 2007-235047). According to this method, the layout area of a memory cell is reduced by sharing a bit line between adjacent columns, and sharing a bit line contact (a contact connecting a source/drain diffusion layer of the transistor with a bit line) of the transistor between adjacent rows (adjacent cells in the same column).
Even by these ideas, however, the layout area of the layout area of a 2T1R memory cell can only be reduced to 10F2 (in the case of sharing a bit line between 4 columns), or 12F2 (in the case of sharing a bit line between 2 columns), and they are larger than 8F2 which is a common layout area of a conventional 1T1R cell.